Embedded firmware documentation generation and maintenance using Doxygen and related tools. Expert skill for API documentation, hardware interface documentation, memory maps, and integration with documentation systems.

Deep integration with JTAG/SWD debug probes for hardware-level debugging and flash programming

GNU linker script generation and optimization for embedded systems. Expert skill for memory layout definition, section placement, multi-image linking, and memory protection configuration.

Embedded memory analysis, optimization, and leak detection

MISRA C compliance checking and static analysis integration

Power consumption measurement and analysis expertise for embedded systems. Integrates with power analyzer tools to measure, profile, and optimize power consumption in battery-powered and energy-efficient designs.

Serial protocol analysis and debugging for common embedded interfaces (I2C, SPI, UART)

Test equipment integration for signal analysis (oscilloscope and logic analyzer)

Embedded unit testing with Unity framework and CMock

USB device and host stack implementation expertise

Specialized skill for Zephyr RTOS development and configuration

Expert skill for AMBA AXI protocol implementation and verification in FPGA designs

Specialized skill for clock domain crossing analysis and synchronizer design in FPGA designs

On-chip debugging skill with ILA, VIO, and related FPGA debug tools

Specialized skill for finite state machine design and optimization in FPGAs

Multi-simulator expertise for functional verification of FPGA designs

Expert skill for C/C++ to RTL conversion using High-Level Synthesis tools

Expert skill for on-chip and external memory interface design in FPGAs

RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.

Specialized skill for creating and debugging SystemVerilog assertions for FPGA verification

Expertise in RTL optimization for FPGA synthesis tools. Analyzes synthesis reports, applies attributes, and guides resource inference for optimal QoR.

Deep expertise in Universal Verification Methodology (IEEE 1800.2) for FPGA verification

Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.

Deep expertise in VHDL language constructs, IEEE 1076 standard compliance, and synthesis coding guidelines. Expert skill for generating synthesizable VHDL code.

A/B testing skill for player segmentation.

Cloth physics skill for softbody dynamics and constraint systems.

Destructible environment skill for fracturing and debris systems.

Godot C# programming skill for .NET integration, scripting patterns, and performance optimization.

GDScript programming skill for Godot Engine, including signals, coroutines, and performance optimization.

Peer-to-peer networking skill for NAT punch-through and relay servers.

Physically-based rendering skill for BRDF models and material workflows.

Procedural sound skill for synthesis and dynamic sound design.

Shader performance optimization skill for instruction counting, GPU profiling, and rendering efficiency.

Texture skill for compression, atlasing, and streaming.

Unity Addressables asset management skill for remote catalogs, content updates, asset bundles, and memory-efficient asset loading.

Unity DOTS/ECS skill for data-oriented design, jobs system, burst compiler optimization, and high-performance gameplay systems.

Unity Profiler skill for performance analysis, frame debugging, memory profiling, and optimization workflows.

Unity UI Toolkit skill for runtime UI development, USS styling, UXML templates, and custom visual elements.

Unity Visual Effect Graph skill for GPU particle systems, procedural effects, and high-performance visual effects.

Expert integration with NVIDIA GPU-accelerated math libraries. Configure cuBLAS tensor core operations, generate cuBLAS GEMM calls, integrate cuDNN layers, handle algorithm selection, and support mixed-precision operations.

Expert skill for GPU debugging using CUDA-GDB and NVIDIA Compute Sanitizer. Detect memory errors, race conditions, uninitialized memory access, validate atomic operations, analyze kernel synchronization issues, and generate debugging reports with recommendations.

Expert skill for CUDA Graph capture and optimization for reduced launch overhead. Capture CUDA operations into graphs, instantiate and execute graph instances, update graph node parameters, profile graph vs stream execution, design graph-friendly kernel patterns, and optimize launch latency for inference.

Deep integration with NVIDIA CUDA toolkit for kernel development, compilation, and debugging. Execute nvcc compilation with optimization flags analysis, generate and validate CUDA kernel code, analyze PTX/SASS assembly output, and configure execution parameters.

High-performance kernel template libraries and DSLs. Generate CUTLASS GEMM configurations, implement Triton kernel definitions, configure epilogue operations, tune tile sizes and warp arrangements, and benchmark against cuBLAS.

Expert skill for automated GPU performance benchmarking and regression detection. Design micro-benchmarks, measure kernel execution time with CUDA events, calculate achieved vs theoretical performance, generate comparison reports, detect regressions in CI/CD, and profile power/thermal characteristics.

AMD HIP and ROCm ecosystem for cross-platform GPU development. Execute hipify conversion tools, generate HIP-compatible kernel code, handle CUDA/HIP API differences, configure ROCm toolchain, and profile with rocprof.

NVIDIA Collective Communications Library integration for multi-GPU operations. Initialize NCCL communicators, execute collective operations, configure communication topologies, profile collective performance, and support RCCL for AMD compatibility.

Expert skill for NVIDIA Nsight Systems and Nsight Compute profiling tools. Configure profiling sessions, analyze kernel reports, interpret occupancy metrics, roofline model data, memory bandwidth bottlenecks, and warp execution efficiency.

NVIDIA hardware video encoding/decoding integration. Configure NVENC encoding parameters, set up NVDEC decoding pipelines, handle codec configurations, integrate with CUDA for pre/post processing, and manage video memory surfaces.

Cross-vendor OpenCL runtime management and kernel development. Query platforms/devices, generate portable OpenCL C kernel code, handle vendor-specific extensions, manage contexts and command queues, compile and cache programs.