Generate and validate issue trees for structured problem solving with MECE validation

Generate workshop agendas, activities, and facilitation guides for elicitation and collaboration sessions

Strategic KPI selection, metric definition, performance dashboard design, and measurement system architecture

Genetic algorithm skill for complex optimization problems with non-linear objectives or discontinuous search spaces

Supply chain master data quality monitoring and improvement skill

Static code analysis, technical debt assessment, engineering velocity metrics

Design and implement data-flow analyses for compiler optimization

Component and system reliability prediction and analysis skill with MTBF/MTTF calculations, failure rate databases, FMEA/FMECA support, fault tree analysis, and accelerated life testing data analysis.

Automated test equipment control and data acquisition skill for hardware validation, with VISA/SCPI instrument communication, test sequence scripting, and measurement uncertainty analysis.

Capacity requirements planning skill with demand-capacity analysis and strategic capacity decisions.

Facility layout optimization skill for material flow minimization and space utilization.

Measurement System Analysis skill for Gage R&R studies with variance component analysis.

Integer and mixed-integer programming skill for combinatorial optimization problems with discrete decision variables.

Network optimization skill for transportation, assignment, and flow problems on graph structures.

Pareto analysis skill for identifying vital few causes and prioritizing improvement efforts.

Single Minute Exchange of Die analysis skill for changeover time reduction.

Takt time and cycle time analysis skill for production line balancing and capacity planning.

Workstation and workspace layout design skill with ergonomic optimization.

Skill for design for manufacturing review and optimization

Skill for first article inspection planning and execution per AS9102

Specialized skill for heat exchanger sizing, rating, and optimization per TEMA standards including shell-and-tube, plate, and air-cooled configurations

Skill for mechanism kinematics, dynamics, and motion analysis

Skill for comprehensive mechanical test plan development and execution support

Skill for compiling and managing LaTeX documents

Create character-specific dialogue with distinct voices, subtext, and naturalistic speech patterns

Optimize and format prompts specifically for AI music generation platforms like Suno and Udio, including platform-specific syntax and tag optimization

Conduct comprehensive literature searches, quality assessments, evidence synthesis, and meta-analyses

GNU linker script generation and optimization for embedded systems. Expert skill for memory layout definition, section placement, multi-image linking, and memory protection configuration.

Power consumption measurement and analysis expertise for embedded systems. Integrates with power analyzer tools to measure, profile, and optimize power consumption in battery-powered and energy-efficient designs.

Test equipment integration for signal analysis (oscilloscope and logic analyzer)

Embedded unit testing with Unity framework and CMock

Expert skill for AMBA AXI protocol implementation and verification in FPGA designs

Specialized skill for finite state machine design and optimization in FPGAs

Multi-simulator expertise for functional verification of FPGA designs

Expert skill for C/C++ to RTL conversion using High-Level Synthesis tools

RTL code quality checking and linting. Runs lint rules, identifies synthesis issues, detects inferred latches, and generates lint reports with waivers.

Specialized skill for creating and debugging SystemVerilog assertions for FPGA verification

Expertise in RTL optimization for FPGA synthesis tools. Analyzes synthesis reports, applies attributes, and guides resource inference for optimal QoR.

Deep expertise in Universal Verification Methodology (IEEE 1800.2) for FPGA verification

Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.

Deep expertise in VHDL language constructs, IEEE 1076 standard compliance, and synthesis coding guidelines. Expert skill for generating synthesizable VHDL code.

Unity DOTS/ECS skill for data-oriented design, jobs system, burst compiler optimization, and high-performance gameplay systems.

Expert skill for GPU debugging using CUDA-GDB and NVIDIA Compute Sanitizer. Detect memory errors, race conditions, uninitialized memory access, validate atomic operations, analyze kernel synchronization issues, and generate debugging reports with recommendations.

Expert skill for CUDA Graph capture and optimization for reduced launch overhead. Capture CUDA operations into graphs, instantiate and execute graph instances, update graph node parameters, profile graph vs stream execution, design graph-friendly kernel patterns, and optimize launch latency for inference.

Deep integration with NVIDIA CUDA toolkit for kernel development, compilation, and debugging. Execute nvcc compilation with optimization flags analysis, generate and validate CUDA kernel code, analyze PTX/SASS assembly output, and configure execution parameters.

Expert skill for automated GPU performance benchmarking and regression detection. Design micro-benchmarks, measure kernel execution time with CUDA events, calculate achieved vs theoretical performance, generate comparison reports, detect regressions in CI/CD, and profile power/thermal characteristics.

NVIDIA Collective Communications Library integration for multi-GPU operations. Initialize NCCL communicators, execute collective operations, configure communication topologies, profile collective performance, and support RCCL for AMD compatibility.

GPU parallel algorithm design patterns and implementations. Implement parallel reduction, scan/prefix sum, histogram, parallel sort algorithms, stream compaction, and work-efficient patterns optimized for specific GPU architectures.

Vulkan compute shader development and pipeline configuration. Generate GLSL/HLSL compute shaders, compile to SPIR-V, configure compute pipelines, manage descriptor sets and resource bindings, implement memory barriers and synchronization.

Warp-level programming and SIMD optimization. Use warp shuffle instructions, voting functions, cooperative groups, warp-synchronous algorithms, and minimize warp divergence for optimal GPU performance.